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ASIC Design Services |
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At FTDI, our experienced engineering team
takes a hands-on approach to ASIC design. Unlike many ASIC design
services, we can offer fully customised designs which can be targeted at
various 0.5 micron and 0.35 micron CMOS processes. For instance,
our FT8U232AM device incorporates custom designed USB transceiver, LDO
regulator, clock multiplier PLL, oscillator and SRAM blocks. We
offer a full turn-key service supplying assembled, tested products at
competitive prices using selected foundries and assembly houses in the
Asia Pacific region.
Not only do we have specialist expertise in USB peripheral, hub and host
design but also in many other areas relating to PC standards (PCI bus
master/target etc.) and embedded design (microcontroller cores and
peripherals).
To complement our ASIC design service, we also offer expertise in
firmware, driver and software development for those projects that
require more than just hardware. The panels below explain our ASIC
design methodology. Contact
Daniel
McCaffrey with details of
your requirements. |
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ASIC Design Stage 1 -
Specification |
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The first stage is to create and agree a specification for the proposed
design including functional blocks, pin count and any special
requirements. This will lead to a quotation and form the basis of
a contract should the quotation be acceptable.
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ASIC Design Stage 2 - Design
and Verification |
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Whenever possible, we try to prototype the design prior to going to
silicon. This gives the advantage of being able to verify that the
design works in it's real environment as well as through simulation.
It also gives a platform for software or firmware development should
this be required prior to first silicon being available. A
prototype usually consists of a PCB with one or more FPGA devices and
other components as required. The design work is usually developed
using VHDL RTL blocks which can be synthesized into FPGA or silicon as
required.
When the customer and FTDI agrees that the prototype's function meets
the specification (within the limits of the prototyping technology) the
customer signs-off the design and FTDI then re-synthesize the design
into the chosen process technology generating a netlist for Stage 3.
The synthesis results of the FPGA version and the silicon version are
compared to ensure that the functionality is the same for both.
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ASIC Design Stage 3 - IC
Layout |
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At this stage, any special IO cells required by the design are
generated. Sometimes special IO cell generation may be done in
parallel with Stage 2 to save time. When the Stage 2 netlist is
available, it is converted into a layout which defines the patterns on
each of the layers of the IC. When the layout is complete, the
device timing is simulated under different process, temperature and
voltage parameters. When these are within specification the layout
is signed-off and GDSII data is generated for the mask generation
process.
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ASIC Design Stage 4 - Mask
Generation |
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Masks are the photographic plates used in the foundry manufacturing
process to create each layer of the device. A typical CMOS process
requires 16 - 18 masks to be generated using the GDSII data from Stage
3.
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ASIC Design Stage 5 -
Manufacture Initial Samples |
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Using the Stage 4 masks, the foundry will produce a batch of engineering
prototype wafers - usually 6 to 12 wafers. Some wafers are kept
for setting up probe and test in preparation for mass production.
The others are cut up into die and assembled into plastic packages.
These are then supplied to the customer to verify their operation in the
customer's application.
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ASIC Design Stage 6 - Mass
Production |
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Once the initial samples have been verified by the customer and
signed-off for mass production, we prepare the tooling and test vectors
ready to manufacture and deliver your device in volume.
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