fifo_mst_top Project Status (09/03/2015 - 12:03:46)
Project File: SP_MC600.xise Parser Errors: No Errors
Module Name: fifo_mst_top Implementation State: Programming File Generated
Target Device: xc6slx16-2csg324
  • Errors:
No Errors
Product Version:ISE 14.3
  • Warnings:
59 Warnings (54 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 2 Failing Constraints
Environment: System Settings
  • Final Timing Score:
176418  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 167 18,224 1%  
    Number used as Flip Flops 167      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 530 9,112 5%  
    Number used as logic 518 9,112 5%  
        Number using O6 output only 283      
        Number using O5 output only 120      
        Number using O5 and O6 115      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 12      
        Number with same-slice register load 0      
        Number with same-slice carry load 12      
        Number with other load 0      
Number of occupied Slices 180 2,278 7%  
Nummber of MUXCYs used 204 4,556 4%  
Number of LUT Flip Flop pairs used 533      
    Number with an unused Flip Flop 378 533 70%  
    Number with an unused LUT 3 533 1%  
    Number of fully used LUT-FF pairs 152 533 28%  
    Number of unique control sets 11      
    Number of slice register sites lost
        to control set restrictions
33 18,224 1%  
Number of bonded IOBs 31 232 13%  
    Number of LOCed IOBs 31 31 100%  
    IOB Flip Flops 19      
    IOB Latches 20      
Number of RAMB16BWERs 8 32 25%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 19 248 7%  
    Number used as ILOGIC2s 19      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 20 248 8%  
    Number used as OLOGIC2s 20      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.65      
 
Performance Summary [-]
Final Timing Score: 176418 (Setup: 176418, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 2 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu 3. Sep 13:15:11 2015038 Warnings (33 new)7 Infos (7 new)
Translation ReportCurrentThu 3. Sep 13:15:30 2015020 Warnings (20 new)2 Infos (2 new)
Map ReportCurrentThu 3. Sep 13:15:51 2015005 Infos (5 new)
Place and Route ReportCurrentThu 3. Sep 13:16:12 201501 Warning (1 new)1 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu 3. Sep 13:16:17 2015003 Infos (3 new)
Bitgen ReportCurrentThu 3. Sep 13:16:24 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentThu 3. Sep 13:16:24 2015

Date Generated: 09/10/2015 - 14:12:21