fifo_mst_top Project Status (09/01/2015 - 17:09:33)
Project File: SP_MC600.xise Parser Errors: No Errors
Module Name: fifo_mst_top Implementation State: Programming File Generated
Target Device: xc6slx16-2csg324
  • Errors:
No Errors
Product Version:ISE 14.3
  • Warnings:
170 Warnings (75 new)
Design Goal: Timing Performance
  • Routing Results:
All Signals Completely Routed
Design Strategy: Performance with IOB Packing
  • Timing Constraints:
X 4 Failing Constraints
Environment: System Settings
  • Final Timing Score:
631073  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 254 18,224 1%  
    Number used as Flip Flops 254      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 462 9,112 5%  
    Number used as logic 451 9,112 4%  
        Number using O6 output only 321      
        Number using O5 output only 37      
        Number using O5 and O6 93      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 11      
        Number with same-slice register load 7      
        Number with same-slice carry load 4      
        Number with other load 0      
Number of occupied Slices 204 2,278 8%  
Nummber of MUXCYs used 108 4,556 2%  
Number of LUT Flip Flop pairs used 517      
    Number with an unused Flip Flop 283 517 54%  
    Number with an unused LUT 55 517 10%  
    Number of fully used LUT-FF pairs 179 517 34%  
    Number of unique control sets 19      
    Number of slice register sites lost
        to control set restrictions
66 18,224 1%  
Number of bonded IOBs 49 232 21%  
    Number of LOCed IOBs 49 49 100%  
    IOB Flip Flops 37      
    IOB Latches 38      
Number of RAMB16BWERs 8 32 25%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 37 248 14%  
    Number used as ILOGIC2s 37      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 38 248 15%  
    Number used as OLOGIC2s 38      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.76      
 
Performance Summary [-]
Final Timing Score: 631073 (Setup: 631073, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 4 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri 28. Aug 09:48:33 2015044 Warnings (38 new)3 Infos (0 new)
Translation ReportCurrentFri 28. Aug 09:48:39 2015076 Warnings (37 new)2 Infos (0 new)
Map ReportCurrentFri 28. Aug 09:49:01 2015041 Warnings (0 new)8 Infos (0 new)
Place and Route ReportCurrentFri 28. Aug 09:49:31 201505 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri 28. Aug 09:49:37 201504 Warnings (0 new)3 Infos (0 new)
Bitgen ReportCurrentTue 1. Sep 17:09:32 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrentFri 28. Aug 09:49:01 2015
WebTalk Log FileCurrentTue 1. Sep 17:09:32 2015

Date Generated: 09/01/2015 - 17:09:33